Fabrication

Six layers, 1.6 mm, ENIG, impedance-controlled, built to JLCPCB stackup JLC06161H-3313. Assembly uses JLCPCB’s parts library; every line on the bill of materials carries an LCSC part number.

Generating the package

fab/generate_jlcpcb.sh

Needs kicad-cli (native or flatpak) and python3. The script will not produce a package if DRC fails — errors, unconnected items and schematic parity are all gated, with zones refilled first. Set SKIP_DRC=1 to override, which is worth doing only when you already know what you are overriding.

Outputs land in fab/jlcpcb/:

Two details in the generator exist because JLCPCB’s uploader rejects the job otherwise. Designator ranges are expanded — C2-C4 becomes C2,C3,C4, because the BOM parser does not expand them and the BOM-to-CPL cross-check then fails on unknown references. And the CPL is filtered down to designators the BOM covers, because DNP parts left in the placement file are treated the same way.

Order settings

Every dielectric is pinned in the board file — material, height and permittivity — so the impedance targets are computed against the stackup that will actually be built, not a generic one.

Impedance targets

Tolerance ±10%, referenced to the adjacent plane. Build to the supplied trace widths. They were computed against JLC06161H-3313, so asking JLCPCB to re-solve for the same impedance would change them for no reason. Krio.kicad_dru carries the length and skew match rules, which are stackup-independent.

Two specifications past the standard tier

Both are deliberate and both cost a tier upgrade. Neither is a mistake to fix.

0.15 mm drills under the SOM connectors

135 vias use a 0.15 mm drill, against JLCPCB’s 0.2 mm standard minimum. They are the fanout under J1 and J2, where the K26’s 0.8 mm pitch leaves no room for a larger hole. Everything else on the board drills 0.2 mm or larger.

Annular ring on 89 vias

The first three sit at or above JLCPCB’s 0.15 mm standard. The remaining 89 fall to 0.129 mm. Enlarging those pads to 0.5 mm would bring them to standard; leaving them requires the same advanced tier the 0.15 mm drills already require, so in practice they cost nothing extra.

annular_width severity is set to error in the project, so these are visible in DRC rather than hidden — and the generator’s DRC gate passes, which means they are within the rules as configured.

What passes without discussion

• DRC — zero violations and zero unconnected items, with zones refilled and schematic parity checked.
• Track and space — netclass floors of 6 mil track and 5 mil clearance sit well inside JLCPCB’s standard capability.
• Edge clearance — 0.381 mm copper-to-edge.
• Bill of materials — 60 lines, 221 parts, all 60 with LCSC part numbers, so nothing gets substituted silently.
• Output format — KiCad’s native Gerber and Excellon output is accepted directly.

The bill of materials

The BOM that goes to assembly is on the assembly page, as a searchable board view — click a part to find it on the PCB, or a footprint to find its row. It is generated from the KiCad project on every documentation build by the same script that builds the upload package, so the published view and the file you order from cannot drift apart.

• Assembly & BOM 2026-08-26

  The bill of materials as a searchable board view — every part cross-referenced against its footprint, its LCSC number and where it sits on the PCB.