J3 — front-end interface

KrIO Connector Specification

The complete J3 pinout, extracted from the design files and cross-checked between schematic and PCB. This is the interface a front-end board has to meet.

Updated 2026-08-25

J3 is where the experiment begins. Everything above it — the K26, boot, both Ethernet ports, PCI Express, power — is fixed on KrIO. Everything below it is the experiment’s own board. A new front end is a card with an HSEC8 socket and whatever analog it needs, and this page is the whole contract it has to satisfy.

Provenance. Every row below is extracted from Krio.kicad_pcb and cross-checked against the netlist exported from Krio.kicad_sch. All 120 of 120 pins agree between the two, as of commit 07e7cfd. Nothing here is transcribed by hand — docs/gen-connector.py regenerates this page and refuses to write it if the schematic and the board disagree. Where this page and the KiCad project differ, the project is authoritative and this page is stale.

Mechanical


Connector	Samtec HSEC8, `Samtec_HSEC8-160-X-X-DV-BL_2x60_P0.8mm_Edge`
Positions	2 × 60, 120 contacts
Pitch	0.8 mm
Mounting	Card edge — J3’s gold fingers are part of KrIO’s own board outline
Mating part	HSEC8 socket on the front-end board

Rows follow the copper. Odd pins are on F.Cu, even pins on B.Cu, and the two pins of a position sit at the same x. This page calls the F.Cu row A and the B.Cu row B; pins 1 and 2 are one position, opposite faces.

The pad field is not uniform. There is a 4.0 mm step between pins 64 and 65 — positions 32 and 33 — where the rest of the connector steps 0.8 mm. That gap is the polarising notch — a slot cut through the card edge, so a front-end board can only be inserted one way round.

Because KrIO is the card rather than the host, the front-end board carries the socket. That is why a front end needs no processor, no boot media and no network interface of its own: it is the daughter board.

The connector

Group	Contacts	Example net
Ground	29	`GND`
HD bank A	20	`HDA14`
HD bank B	24	`HDB05`
HD bank C	24	`HDC18`
HP differential	12	`HPB_CLK0_P`
Power — 3.3 V	4	`+3V3_PL`
Power — 12 V	4	`+12Vin`
I²C	2	`SCL`
Present detect	1	`MIO75`

Row A is the front face (F.Cu), row B the back (B.Cu). The two contacts of a position sit at the same x on opposite faces, so pins 1 and 2 are one position seen from either side. Hover any contact for its pin number and net.

What crosses J3

Group	Pins
Ground	29
HD bank A	20
HD bank B	24
HD bank C	24
HP differential	12
Power — 3.3 V	4
Power — 12 V	4
I²C	2
Present detect	1

HD banks A, B and C are single-ended I/O to the K26’s high-density banks — HDA lands on SOM socket J1, HDB and HDC on J2. Direction is set per pin inside the K26’s I/O banks, not by the carrier, so this table names nets rather than inputs and outputs. Nets suffixed _CC sit on clock-capable pins; put a clock anywhere else and lose it.

HP differential is five differential pairs plus a clock pair — HPB00_CC through HPB04, and HPB_CLK0 — routed to the SOM’s high-performance bank on J2. These are the pairs for anything that has to be matched or fast.

Present detect is MIO75 on pin 69, pulled on KrIO and brought out to the PS, so a front-end board that ties it appropriately is visible to software.

I²C is the PS bus on pins 105 and 106, for front-end identification and slow control.

Power

Rail	Pins	Where it comes from
`+3V3_PL`	109–112	Generated on KrIO by U33 (TPSM86637RCGR), enabled by the SOM’s `VCCOEN_PL`. It is the PL bank VCCO rail, which is what sets the HD I/O level.
`+12Vin`	115–118	The board’s 12 V input rail, arriving at KrIO’s 6-pin PCIe power connector (U23) through a TVS clamp.
`GND`	29 pins	Distributed through the field rather than bunched at the ends.

+12Vin is upstream of the eFuse. KrIO’s TPS259260 (U24) takes +12Vin in and produces +12V for the rest of the board; J3 sits on the input side. A front end drawing from pins 115–118 is drawing from the unprotected rail and needs its own protection.

Pin table

Pin	Row	Net	Group
1	A	`GND`	Ground
2	B	`GND`	Ground
3	A	`HPB_CLK0_P`	HP differential
4	B	`HPB02_P`	HP differential
5	A	`HPB_CLK0_N`	HP differential
6	B	`HPB02_N`	HP differential
7	A	`GND`	Ground
8	B	`GND`	Ground
9	A	`HPB00_CC_P`	HP differential
10	B	`HPB03_P`	HP differential
11	A	`HPB00_CC_N`	HP differential
12	B	`HPB03_N`	HP differential
13	A	`GND`	Ground
14	B	`GND`	Ground
15	A	`HPB01_P`	HP differential
16	B	`HPB04_P`	HP differential
17	A	`HPB01_N`	HP differential
18	B	`HPB04_N`	HP differential
19	A	`GND`	Ground
20	B	`GND`	Ground
21	A	`HDA14`	HD bank A
22	B	`HDA08_CC`	HD bank A
23	A	`HDA13`	HD bank A
24	B	`HDA07`	HD bank A
25	A	`HDA12`	HD bank A
26	B	`HDA06`	HD bank A
27	A	`HDA02`	HD bank A
28	B	`HDA03`	HD bank A
29	A	`GND`	Ground
30	B	`GND`	Ground
31	A	`HDA01`	HD bank A
32	B	`HDA04`	HD bank A
33	A	`HDA00_CC`	HD bank A
34	B	`HDA05`	HD bank A
35	A	`HDA09`	HD bank A
36	B	`HDA15`	HD bank A
37	A	`HDA10`	HD bank A
38	B	`HDA18`	HD bank A
39	A	`GND`	Ground
40	B	`GND`	Ground
41	A	`HDA11`	HD bank A
42	B	`HDA19`	HD bank A
43	A	`HDA16_CC`	HD bank A
44	B	`HDA20`	HD bank A
45	A	`HDB05`	HD bank B
46	B	`HDB11`	HD bank B
47	A	`HDB04`	HD bank B
48	B	`HDB10`	HD bank B
49	A	`GND`	Ground
50	B	`GND`	Ground
51	A	`HDB03`	HD bank B
52	B	`HDB09`	HD bank B
53	A	`HDB02`	HD bank B
54	B	`HDB08_CC`	HD bank B
55	A	`HDB01`	HD bank B
56	B	`HDB07`	HD bank B
57	A	`HDB00_CC`	HD bank B
58	B	`HDB06`	HD bank B
59	A	`GND`	Ground
60	B	`GND`	Ground
61	A	`HDB18`	HD bank B
62	B	`HDB12`	HD bank B
63	A	`HDB19`	HD bank B
64	B	`HDB13`	HD bank B
65	A	`HDB20`	HD bank B
66	B	`HDB14`	HD bank B
67	A	`HDB21`	HD bank B
68	B	`HDB15`	HD bank B
69	A	`MIO75`	Present detect
70	B	`GND`	Ground
71	A	`HDB22`	HD bank B
72	B	`HDB16_CC`	HD bank B
73	A	`HDB23`	HD bank B
74	B	`HDB17`	HD bank B
75	A	`HDC18`	HD bank C
76	B	`HDC12`	HD bank C
77	A	`HDC19`	HD bank C
78	B	`HDC13`	HD bank C
79	A	`GND`	Ground
80	B	`GND`	Ground
81	A	`HDC20`	HD bank C
82	B	`HDC14`	HD bank C
83	A	`HDC21`	HD bank C
84	B	`HDC15`	HD bank C
85	A	`HDC22`	HD bank C
86	B	`HDC16_CC`	HD bank C
87	A	`HDC23`	HD bank C
88	B	`HDC17`	HD bank C
89	A	`GND`	Ground
90	B	`GND`	Ground
91	A	`HDC05`	HD bank C
92	B	`HDC11`	HD bank C
93	A	`HDC04`	HD bank C
94	B	`HDC10`	HD bank C
95	A	`HDC03`	HD bank C
96	B	`HDC09`	HD bank C
97	A	`HDC02`	HD bank C
98	B	`HDC08_CC`	HD bank C
99	A	`GND`	Ground
100	B	`GND`	Ground
101	A	`HDC01`	HD bank C
102	B	`HDC07`	HD bank C
103	A	`HDC00_CC`	HD bank C
104	B	`HDC06`	HD bank C
105	A	`SCL`	I²C
106	B	`SDA`	I²C
107	A	`GND`	Ground
108	B	`GND`	Ground
109	A	`+3V3_PL`	Power — 3.3 V
110	B	`+3V3_PL`	Power — 3.3 V
111	A	`+3V3_PL`	Power — 3.3 V
112	B	`+3V3_PL`	Power — 3.3 V
113	A	`GND`	Ground
114	B	`GND`	Ground
115	A	`+12Vin`	Power — 12 V
116	B	`+12Vin`	Power — 12 V
117	A	`+12Vin`	Power — 12 V
118	B	`+12Vin`	Power — 12 V
119	A	`GND`	Ground
120	B	`GND`	Ground